Input/Output Processing Pipe's Link Connection x Control (OPPLC0CTL) – Offset 980
SRST bit is not affected by stream reset.
Bit Range | Default | Access | Field Name and Description |
30:24 | - | - | Reserved |
23:20 | 0h | RW | Stream Number (STRM) This value reflects the Tag associated with the data being transferred on the link.
0000=Reserved (Indicates Unused)
0001=Stream 1
...
1110=Stream 14
1111=Stream 15
Input Stream:
When an input stream is detected on any of the SDIx signals that match this value, the data samples are loaded into the FIFO associated with this descriptor. Note that while a single SDIx input may contain data from more than one stream number, two different SDIx inputs may not be configured with the same stream number.
Output Stream:
When data controlled by this descriptor is sent out over the link, it will have this stream number encoded on the SYNC signal. |
19:2 | - | - | Reserved |
1 | 0b | RW/V | Stream Run (RUN) When set to 1 the DMA engine associated with this stream will be enabled to transfer data between FIFO and main memory. The SSYNC bit must also be cleared in order for the DMA engine to run. For output streams, the cadence generator is reset whenever the RUN bit is set.
When cleared to 0 the DMA engine associated with this stream will be disabled. Hardware will report a 0 in this bit when the DMA engine is actually stopped. Software must read a 0 from this bit before modifying related control registers or restarting the DMA engine. |
0 | 0b | RW/V | Stream Reset (SRST) Writing a 1 causes the corresponding stream to be reset. The Stream Descriptor registers (except the SRST bit itself) and FIFO's for the corresponding stream are reset. After the stream hardware has completed sequencing into the reset state, it will report a 1 in this bit. Software must read a 1 from this bit to verify that the stream is in reset.
Writing a 0 causes the corresponding stream to exit reset. When the stream hardware is ready to begin operation, it will report a 0 in this bit. Software must read a 0 from this bit before accessing any of the stream registers. The RUN bit must be cleared before SRST is asserted. |