Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
ID | Date | Version | Classification |
---|---|---|---|
615146 | 08/09/2019 | 1.2 | Public |
LPC Generic IO Range 1 (LGIR1) – Offset 84
LPC Generic IO Range 1.
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
30:24 | - | - | Reserved
|
23:18 | 00h | RW | Address[7:2] Mask (ADDRESS_7_2_MASK) A 1 in any bit position indicates that any value in the corresponding address bit in a received cycle will be treated as a match. The corresponding bit in the Address field, below, is ignored. The mask is only provided for the lower 6 bits of the DWord address, allowing for decoding blocks up to 256 bytes in size. |
17:16 | - | - | Reserved
|
15:2 | 0000h | RW | Address[15:2] (ADDRESS_15_2) DWord-aligned address. Note that PCH does not provide decode down to the word or byte level. |
1 | - | - | Reserved
|
0 | 0b | RW | LPC Decode Enable (LPC_DECODE_ENABLE) When this bit is set to 1, then the range specified in this register is enabled for decoding to LPC. |