Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
ID | Date | Version | Classification |
---|---|---|---|
615146 | 08/09/2019 | 1.2 | Public |
PCI Express Configuration (PCIEDBG) – Offset 324
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:29 | 000b | RW | Transmit nFTS Adder (TXNFTSADD) This field specifies the 1-based number of additional nFTS sets to be transmitted to the opposite device on TXL0s exit on top of the actual number of nFTS sets. |
28:26 | - | - | Reserved
|
25:24 | 10b | RW | Configuration Field (LGCLKSQEXITDBTIMERS) BIOS may program this register bit. |
23:15 | - | - | Reserved
|
14 | 0b | RW | Configuration Field (CTONFAE) BIOS may program this register bit. |
13:8 | - | - | Reserved
|
7 | 0b | RW | Configuration Field (SQOL0) BIOS may program this register bit. |
6 | - | - | Reserved
|
5 | 0b | RW | Configuration Field (SPCE) BIOS may program this register bit. |
4 | 0b | RO/V | Lane Reversal (LR) This register reflects the PCIe* Lane Reversal Configuration soft strap. It defines if the Root Port associated with a PCIe* Controller is configured with Lane Reversal enabled or disabled |
3:0 | - | - | Reserved
|